The numbers you povided are for output/generation. Input is around 5-20 thousand for Astra, and 16-60k for Luna. So a few hundred times faster.
Most of the tokens consumed by agents is reading stuff - docs, tool outputs, code etc. Previewing a content of a dumb single page of html is a few thousand tokens.
If you use claude or some other harness you can ask it how many cache writes/input tokens are there in avg session, and how much time it would take if preprocessing speed was just 60 tok/s.
I would guess the assumption is that "agentic work" should be happening asynchronously in the background on a machine that's also used for foreground interactive work, where the slower the inference is, the longer the machine's GPU and [V]RAM are "hogged" by it at a time, and so the more the machine's performance seems to degrade.
I have a couple of V100 and am working on making Flash Next really fast on them. So far I am at like 193 t/s decode on a specialist 3-bit quant. On shorter prompts. Around 109 t/s on a ggml/llama fork at depth before I gave up and started writing the engine from scratch. I guess I will end at about 220-250 t/s at 128k context size with about 3K prefill on these cards.
https://stealthgoat.com/deepswe-flash-next.html (Total AI pile). I benched this quant for 3 days on DeepSWE in a 16GB VRAM gaming PC. It held 90 t/s on avg I think. It’s solid. The authors claims of minimal intelligence loss hold. Sorry it renders bad in mobile will fix it soon.
It feels great to have a local model ripping at these speeds. I now use Flash NeXT as an active agent managing part of the engine build process and let it do some coding on easier chores :)
Not sure if the measurement method used for this is actually valid or reliable enough, but for reference, Codex 6.1 Sol Standard runs at 19.9 tok/s according to a benchmark I recently saw: https://www.reddit.com/r/codex/s/b4mUszSOv1
I wonder when we will start seeing small commercial accelerators integrated with NVMes; could potentially use far more bandwidth than typical NVMe drive can push thru the four lanes.
Given that you'd have probably a lot more capacity just to get to required bandwidth it could be used to switch very quickly between models (as all stored there would essentially be "loaded")
Seems like a useful innovation on the desktop level, but on the server level, isn't it already pretty normal to see machines with 24x high-performance (i.e. individually high-bandwidth) NVMe drives in them, that can then be used in software RAID0 to achieve pretty massive read bandwidth?
Well, it's not my field, but pci5.0 x4 drives are the fastest I found with a quick Google. So 24 of those would top out at ~400 GB/s. That's also where HBF starts out, for one device. The higher grades are faster, but maybe NVMe will be as fast by the time they are out.
But the win here on servers is almost certainly power. High speed signals are power hungry, and the power scales with the length of the wire. HBF is designed to go in the same package as the GPU, so the distance is much shorter than with discrete drives.
There are many of these stream-experts-from-SDDD projects now. What's needed is a guide to all of them and maybe for someone to take the best features of each of them and merge them into one uber project.
My impression based on a cursory look at the research is that the caching algorithm is absolutely vital, non-obvious, model-dependent, and potentially prompt-dependent to make sure you're holding onto the right experts.
Based on how vibe-coded this whole thing is, I’m guessing the newer models weren’t in the training data and the agent just picked what it knew existed.
This could be a game changer for me. The best I've been able to do so far is ~8 tok/s with Qwen 35B A3B, 32GB RAM. But then again I just got an OpenCode Go plan yesterday and have yet to figure if I can even consume my quota on DeepSeek Flash as the need to plan things well is bottlenecking me. Might be a while before I try the local thing again.
I have one of my own. My reason for this is that you can get up to 2x performance compared to llama.cpp on the same model weights. It is optimized for single model to serve it well.
llama.cpp is a generalized inference engine; therefore, model-specific optimizations should remain outside its core architecture. When developing a bespoke inference application, it is standard practice to fuse operations and heavily optimize the compute kernels for the specific target model.
llama.cpp has strict policies on AI-assisted contributions. Most of these specialization projects are done by coding agents. So llama.cpp won't take them (which is fair).
I did, the sd.cpp take too much time on my laptop to generate image, the issue is known and it did not seem like it gonna be resolved, so I build my own, and that's why https://github.com/netdur/qwen-image-cplus
Most of these custom engines exist because the more general purpose projects make contributing much harder than maintaining a custom engine (somewhat understandably). Consequently they take forever to adopt optimizations, and it is somewhat pointless if llama.cpp or vllm only reach performance parity with custom engines when the LLM architectures being optimized for are no longer the best ones.
The benefit of llama.cpp etc is just ease of use for people not already familiar with the local AI landscape.
> Using a GPU has, once, caused a driver reset that took the desktop with it.
Only once? This has happened to me so many times with LLM-assisted development. I was writing an OCR engine and pathological shapes would cause OOM that would take the display out. On other occasions, the LLM would try to load 24GB of bf16 weights onto a 16GB GPU without understanding the consequences.
Have to encode this in logic: keep some space reserved for the display, and check before allocation. But some errors are bound to slip through.
---
Inspired by DwarfStar4 and Strata, I am trying to build my own gemma4-specific inference engine designed to run on gfx1201.
It is a lot of work. You cannot simply vibecode one in two days.
It will be when done. I have a lot of stuff in the works and switch between them based upon my current interest. I like plotting and writing stories and Gemma is one of the nicer writers.
The goal is to get the 31B working on a 16GB card. Which means weights have to be < 4 bits. The 9070 XT has wmma support for int4. Which doubles compute performance on pp compared to i8/fp8. tg is limited by bandwidth.
I think fits in a RAM is the first step, a real practical question is if in the mean time you can still use the machine for basic tasks like use browser watch YouTube/VS Code etc.
Amazing to me that something as wild as this is now basically a trope.
I don't mean this negatively; open weights AI and open source tooling is about the only thing that gives me hope.
The fact that there are dozens of these things hints at the beginning of the dull normalisation of openly available, non-monopoly AI tools, which is what is needed if we are all to survive.
I can't justify this at all, but it feels like there's headroom in the currently-available hardware, which the current shortage will increasingly force us to optimise into. Then when the choke-point relaxes the upper bound of what's achievable will be even higher than it would have been.
There's plenty of optimisations still possible if you optimise for specific GPU families. Eg see Hipfire[1] and q38rocm/HaloPFX[2], they're so much more faster than llama.cpp for consumer AMD GPUs.
OK, yes, this I do agree with but I was mostly factoring these in (because I did that research a couple of weeks ago while speccing out a hypothetical R9700 box)
One of the architectural changes expected in the next series of Qwen models appears to be well suited to SSD streaming.
But also, there probably still is a lot of room for tuning and better utilizing the streaming capability, e.g. better speculative streaming to have the activated experts loaded in RAM by the time they're needed.
Same as big data centers siphoned up all the SSDs before their prices became reasonable for consumers, same with HDDs, or RAM every generation. They’ll be high before they’ll be reasonable, and then they’ll be cheap once their next generation comes along.
The obvious thing that I can coming see is high bandwidth flash, which as far as I know is under active development by multiple companies.
From what I've read one architecture is basically RAID0 at the flash chip/chiplet or PCB level, combining many fast flash chips into one wide channel and then turning that into a wide fast streaming storage system. Fast as in competitive with DRAM, at least for streaming a lot of data, which is what most AI inference wants.
Flash, even very fast flash, is much cheaper than DRAM per GB.
I'd like a specialized local inference node consisting of 2TB high bandwidth flash, 16-32GB of DRAM (for attention and other state), and a big TPU. That could run frontier size models in something the size of a large mini PC like an Intel Nuc. The lower cost of flash would probably move most of the cost to the processor(s).
I wonder how feasible it would be to DIY a board layout for basically RAID0 flash that's pretty good? A bunch of flash chips in parallel. Use something like a cheap fast ARM or RISC-V chip as the flash controller and have it do striping and present itself as an abstract drive over a thunderbolt or PCIe interface.
Currently, the fastest way to connect flash is via PCIe 5.0 x4. Right?
That's ~16 GB/s. Even if you do RAID0 of 4 such drives, that would get you 64GB/s. That's not a lot. Compare that to 1792 GB/s for RTX 5090: it's 100x faster than NVMe flash.
That's why I think you'd have to do something board-level at least, not just plugging existing modules or SSDs together. You'd have to stuff flash chips on a novel board with a novel controller architecture.
The work I've seen at places like Samsung and Intel is chip level.
Why hasn't this been done already? No market until recently. Existing flash is fast enough for SSD use cases, and making it fast enough to compete with DRAM makes it more expensive. Meanwhile it's not a true DRAM replacement because it's slow to write, slower than DRAM for true random access, and can wear out with many write cycles. It only makes sense for applications that are read-mostly, streaming, and require huge data, and that was a small market until AI.
Correct, but that's comparable to streaming from CPU memory to GPU memory, which seems to work OK for MOE models. Then again, if model sizes are so large that you need SSDs, maybe not so much.
I think this is still the tip of the iceberg in terms of this method.
There is no particular requirement for this to be limited to a single SSD.
What happens when someone makes a GPU Card with enough SSDs attached to feed every RAM chip individually.
PS: There's heat you've got to worry about a bit, especially in very high speed drives, but that's about it (practically speaking). Bit rot prevention consumes some write cycles too but that is minuscule in comparison.
3eb7988a1663 | 22 hours ago
Which seems sufficient for mortals who are not running gas town, but want a local model.
kolinko | 21 hours ago
serf | 20 hours ago
may I ask why?
oai luna runs at 60-70 toks/s; astra runs around 35-45 , are you just worried that your agentic work can't spread across a lot of parallel work?
kolinko | 20 hours ago
Most of the tokens consumed by agents is reading stuff - docs, tool outputs, code etc. Previewing a content of a dumb single page of html is a few thousand tokens.
If you use claude or some other harness you can ask it how many cache writes/input tokens are there in avg session, and how much time it would take if preprocessing speed was just 60 tok/s.
jcmfernandes | 5 hours ago
derefr | 20 hours ago
teaearlgraycold | 20 hours ago
bitexploder | 17 hours ago
https://stealthgoat.com/deepswe-flash-next.html (Total AI pile). I benched this quant for 3 days on DeepSWE in a 16GB VRAM gaming PC. It held 90 t/s on avg I think. It’s solid. The authors claims of minimal intelligence loss hold. Sorry it renders bad in mobile will fix it soon.
It feels great to have a local model ripping at these speeds. I now use Flash NeXT as an active agent managing part of the engine build process and let it do some coding on easier chores :)
kolinko | 13 hours ago
brcmthrowaway | 21 hours ago
[OP] khalidkhair | 21 hours ago
InsidiousWombat | 22 hours ago
Given that you'd have probably a lot more capacity just to get to required bandwidth it could be used to switch very quickly between models (as all stored there would essentially be "loaded")
kadoban | 22 hours ago
ajb | 20 hours ago
derefr | 20 hours ago
ajb | 5 hours ago
But the win here on servers is almost certainly power. High speed signals are power hungry, and the power scales with the length of the wire. HBF is designed to go in the same package as the GPU, so the distance is much shorter than with discrete drives.
swerner | 15 hours ago
KerrAvon | 21 hours ago
Espressosaurus | 16 hours ago
It doesn't look like a solved problem yet.
purplecats | 21 hours ago
doublerabbit | 21 hours ago
trollbridge | 21 hours ago
Maybe next you can run an LLM off of some old MFM drives
Havoc | 14 hours ago
jurgenburgen | 10 hours ago
kadoban | 20 hours ago
droidjj | 20 hours ago
x-complexity | 19 hours ago
https://hfviewer.com/compare/qwen3.6-27b-vs-qwen3.8-27b
suprjami | 20 hours ago
What a waste of time.
Strata already does this with Qwen3.8-Flash-Next: https://github.com/Niko1221/Strata
DiabloD3 | 19 hours ago
kennywinker | 17 hours ago
Are we hallucinating now too, not just the bots?
mikodin | 5 hours ago
DiabloD3 | 4 hours ago
tcdent | 17 hours ago
xpct | 17 hours ago
skeledrew | 19 hours ago
MadameMinty | 15 hours ago
https://github.com/prabanta-dev/janas <- this, focuses on Qwen3-Next-80B-A3B.
https://github.com/Niko1221/Strata <- Qwen3.8-Flash-Next. I use this (tuned) and I cannot understate how satisfied I am.
https://github.com/antirez/ds4 <- DeepSeek 4 family + more.
MadameMinty | 11 hours ago
zelcon | 19 hours ago
I don’t want to bother reading anything sub-Fable, and this one looks sub-Fable.
jdb9001 | 18 hours ago
croes | 18 hours ago
sercand | 14 hours ago
vorticalbox | 11 hours ago
sercand | 11 hours ago
utilize1808 | 9 hours ago
am17an | 6 hours ago
netdur | 6 hours ago
cyanydeez | 12 hours ago
dominotw | 6 hours ago
halJordan | an hour ago
hgoel | 9 hours ago
The benefit of llama.cpp etc is just ease of use for people not already familiar with the local AI landscape.
sieve | 16 hours ago
Only once? This has happened to me so many times with LLM-assisted development. I was writing an OCR engine and pathological shapes would cause OOM that would take the display out. On other occasions, the LLM would try to load 24GB of bf16 weights onto a 16GB GPU without understanding the consequences.
Have to encode this in logic: keep some space reserved for the display, and check before allocation. But some errors are bound to slip through.
---
Inspired by DwarfStar4 and Strata, I am trying to build my own gemma4-specific inference engine designed to run on gfx1201.
It is a lot of work. You cannot simply vibecode one in two days.
mstkllah | 15 hours ago
sieve | 14 hours ago
The goal is to get the 31B working on a 16GB card. Which means weights have to be < 4 bits. The 9070 XT has wmma support for int4. Which doubles compute performance on pp compared to i8/fp8. tg is limited by bandwidth.
nicman23 | 10 hours ago
aboardRat4 | 14 hours ago
nicman23 | 10 hours ago
LeoisNotAI | 13 hours ago
chernoby | 13 hours ago
dofm | 13 hours ago
I don't mean this negatively; open weights AI and open source tooling is about the only thing that gives me hope.
The fact that there are dozens of these things hints at the beginning of the dull normalisation of openly available, non-monopoly AI tools, which is what is needed if we are all to survive.
tommica | 12 hours ago
regularfry | 12 hours ago
dofm | 12 hours ago
There may well be headroom within the software/architecture of LLMs but once you get down to streaming tokens, it is kind of running into the physics?
d3Xt3r | 10 hours ago
[1] https://github.com/warpfront/hipfire
[2] https://github.com/julianmb/q38rocm
dofm | 8 hours ago
hgoel | 9 hours ago
But also, there probably still is a lot of room for tuning and better utilizing the streaming capability, e.g. better speculative streaming to have the activated experts loaded in RAM by the time they're needed.
GeekyBear | 12 hours ago
> Asianometry: High Bandwidth Flash Is Coming
https://www.youtube.com/watch?v=3nTpW52nioI
7speter | 8 hours ago
zardo | 4 hours ago
tourmalinetaco | 3 hours ago
dofm | 46 minutes ago
I'd always assumed that the first generation of SSDs were really tested on consumers.
conorcleary | 12 hours ago
api | 8 hours ago
From what I've read one architecture is basically RAID0 at the flash chip/chiplet or PCB level, combining many fast flash chips into one wide channel and then turning that into a wide fast streaming storage system. Fast as in competitive with DRAM, at least for streaming a lot of data, which is what most AI inference wants.
Flash, even very fast flash, is much cheaper than DRAM per GB.
I'd like a specialized local inference node consisting of 2TB high bandwidth flash, 16-32GB of DRAM (for attention and other state), and a big TPU. That could run frontier size models in something the size of a large mini PC like an Intel Nuc. The lower cost of flash would probably move most of the cost to the processor(s).
I wonder how feasible it would be to DIY a board layout for basically RAID0 flash that's pretty good? A bunch of flash chips in parallel. Use something like a cheap fast ARM or RISC-V chip as the flash controller and have it do striping and present itself as an abstract drive over a thunderbolt or PCIe interface.
SlavikCA | 8 hours ago
That's ~16 GB/s. Even if you do RAID0 of 4 such drives, that would get you 64GB/s. That's not a lot. Compare that to 1792 GB/s for RTX 5090: it's 100x faster than NVMe flash.
api | 7 hours ago
The work I've seen at places like Samsung and Intel is chip level.
Why hasn't this been done already? No market until recently. Existing flash is fast enough for SSD use cases, and making it fast enough to compete with DRAM makes it more expensive. Meanwhile it's not a true DRAM replacement because it's slow to write, slower than DRAM for true random access, and can wear out with many write cycles. It only makes sense for applications that are read-mostly, streaming, and require huge data, and that was a small market until AI.
davrosthedalek | 3 hours ago
Lerc | 13 hours ago
There is no particular requirement for this to be limited to a single SSD. What happens when someone makes a GPU Card with enough SSDs attached to feed every RAM chip individually.
0x073 | 12 hours ago
mrleinad | 11 hours ago
alexpotato | 10 hours ago
e.g. each expert lives on one node of the network and the model gets streamed.
sheepscreek | 10 hours ago
unrented7977 | 10 hours ago
sheepscreek | 6 hours ago
PS: There's heat you've got to worry about a bit, especially in very high speed drives, but that's about it (practically speaking). Bit rot prevention consumes some write cycles too but that is minuscule in comparison.
justsomehnguy | 4 hours ago
yaanfpv | 9 hours ago